DfT for achieving 0 DPPB, are we there yet?

Tom Waayers

NXP semiconductors


Achieving 0 dppb (defective parts per billion) in testing or manufacturing requires a very high level of precision and accuracy, and is a challenging goal. It requires a thorough understanding of the product and its design, as well as the manufacturing process and any potential sources of variability or error. To achieve 0 dppb, it is necessary to implement advanced testing and measurement techniques, such as specialized instrumentation and calibration techniques, to ensure that the product is consistent and meets the required specifications. It also requires careful process control and monitoring, as well as rigorous quality assurance and control measures to identify and address any issues that may arise during the manufacturing process. Consequently, achieving 0 ppb requires a robust design for test (DFT) strategy to ensure that the product can be easily and accurately tested and debugged. This involves testability features into the product, as well as test equipment and procedures to accurately measure and evaluate the product's performance. The required high levels of precision and quality come with a cost. The cost of quality is not limited to the cost we incur to produce a certain quality level. It needs a mindset to produce quality in which DfT is applied to increase quality, as well as to prevent costs and further reduce costs in the product life cycle.

This talk will introduce the evolution in DfT to address the challenges to achieve 0 DPPB. It will discuss cost of quality and the role of DfT in cost prevention. It will address the possible impact of functional safety and security features, as well as further market demands like speed and flexibility in design integration.

Short Bio

Tom Waayers is part of the central Design Enablement team in NXP semiconductors. NXP is a major player in the semiconductor industry, with a wide range of products. Amongst others, NXP is a leading provider of solutions for the automotive industry, including microcontrollers, power management ICs, and secure in-vehicle communication.
Tom received the MSc degree in Electrical Engineering from Technical University in Eindhoven. In 1995 he started working on Design for Test methodology in Philips research laboratories. He contributed in IEEE Std 1500 and is co-author of The Core Test Wrapper Handbook-Springer.
Tom is NXP notable inventor with 17 US patents and presented multiple conference papers on test. Since 2014 he is leading the DfT and Test innovation and design automation in NXP semiconductors.